A Multithreaded Compiler Optimization Technology with Low Power
Rongcai Zhao · 2002
A theoretic model and method is proposed to decrease power consumption effectively by reducing execution frequency on multithreaded architecture in this paper. At first, the computation model is studied to recognize the thread which can be executed at lower frequency, and the factor is computed to slow down the frequency. Then, an algorithm and policy of compiler optimization combining with thread partition for low power is given based on the analysis of application program. This model and method can be used to exploit TLP (thread level parallelism) and decrease the power consumption effectively for the multithreaded multiprocessor architecture with scalable execution frequency.