Mappings of Gate Level Faults to Register Transfer Level Faults
Jianhui Jiang · Journal of Tongji University · 2004
Fault models are very important for circuit fault testing,fault tolerance design and verification,performance assessment based fault injection.This paper presents an experiment on the study of the mapping relationship between register transfer level (RTL) faults and gate level faults. In this experiment,a group of commercial 74 family integrated circuits and ISCAS85 benchmark circuits are used as RTL primitive components.The experimental results show that it cannot obtain the expected gate level fault coverage if only single erroneous primary output is considered for most circuits,it is not suitable for RTL circuits to implement by XOR gate,AOI gate or OAI gate and different functional RTL circuits must consider different number of primary output errors,and the RTL circuits with same function but different local logical implementations can consider the same number of primary output errors.