Design of Low Hardware-cost AES
Weiping Jing · Jisuanji gongcheng · 2005
Small area is required for cipher chips used in portable devices such as smart card and PDA etc.The requirement for hardware resource is dramatically decreased by careful optimization of the AES algorithm.The optimized AES architecture is described by Verilog HDL and implemented with Altera APEX20K device.The validated FPGA prototype integrates both the encryption and decryption modes and all the three kinds of key length,which is suitable for the future VLSI implementation of the AES.