SLC/MLC NAND FLASH Controller VLSI Design with BCH Encoder and Decoder
Haiyan Zhou · Modern Electronics Technique · 2009
For the need of low cost per bit and high storage density in market,a SLC/MLC NAND FLASH controller included in a SoC processor chip based on ARM926EJ is designed.A 4-EC BCH Error-Correction Code(ECC) is designed for correcting the random bit errors of the FLASH memory chip,which is suitable for the randomly bit errors property of the NAND-type FLASH memory.Various kinds of NAND FLASH memory could be supported by this single controller.In addition,an efficient VLSI architecture for encoding and decoding BCH codes with the Berlekamp-Massey algorithm are presented.The speed bottleneck in the Berlekamp-Massey algorithm is eliminated via a low complexity key equation solver using a simplified B-M algorithm.The chip is implemented with SMIC 0.13 μm CMOS process.Test results show the designed circuit can fully comply with the system specifications and show the good performances.