Design of High-Speed Low-Power Clocked Comparator
IC Design · Semiconductor Technology · 2008
A high-speed low-power clocked comparator was designed by analyzing all sorts of comparators,with emphasis on optimizing the speed and power of the comparator.Based on 0.35 μm SMIC n-well technology,the circuit was simulated by Cadence Spectre.Results show that the maximum operating frequency of the comparator is 200 MHz,resolution is 0.3 mV,and power consumption is only 0.4 mW at 3.3 V.