A New FPGA Realization of the Full-Pipeline of Conversion from Fixed-point to Floating Point
Luo Jin-xuan · Microelectronics & Computer · 2012
In this paper,completely independent and bottom-level design is conducted by utilizing FPGA device,realizing conversion from fixed-point to floating point.A completely new method is proposed for such realization to output data by taking 3 clock cycles.In this method,subtraction calculation instead of logarithm calculation is adopted,occupying 1% logic resources and avoiding the restrictions of using IP core and laying a foundation for follow-up ASIC design.