A STUDY ON THEORYAND APPLICATION OF DIGITAL NATURAL SAMPLING BASED SPWM
Jie Shi · Proceedings of the CSEE · 2005
A novel scheme of digital natural sampling based SPWM (sinusoidal PWM) is presented which is achieved by CPLD (complex programming logic device). This scheme is trusty and easily integrated as digital circuit, programmable as microprocessor, and rapid in response and with a precision as natural sampling SPWM. The digitization of sinusoidal modulation signals us(t) however, may cause a pulse width error in the SPWM output. A positive slope of us(t) makes the plus pulse width wider, and a negative one makes the minus pulse width wider. All these errors can be equivalent to adding an odd harmonic to the fundamental. There are some pulse competition in the digital natural sampling based SPWM. The study inchcates that the best error pulse width and the competition pulse width are proportional to the sampling period to us(t) and the modulation degree of SPWM; the number of competition pulse are dependent on the slop of us(t). A method for eliminating the competition pulses is presented. Satisfactory experiment results were obtained in a single-phase 4kVA voltage source inverter operating in 4-multiple SPWM.