FPGA Implementation of Systolic Array for Modular Multiplication Using a Fine-grained Approach
Hongyi Chen · Microelectronics & Computer · 2005
A fine-grained mapping approach is proposed according to the analysis of the detailed configurable logic block structure of FPGA device, and it is applied to the design of a systolic array for modular multiplication based on FPGA. Without performance losses, the logic resources consumed by the systolic array are reduced to one-third of its original requirement. By exploiting this approach, it's possible to implement a 1024-bit modular multiplier on a 200K gate low-cost FPGA, which can perform 20 1024-bit RSA signature operations per second. Implemented on a high-end FPGA, the modular multiplier can obtain a performance up to 40 signature operations per second.