Design of a Reconfigurable Low Power Multiply-Accumulator
Yongwei Li, Jiang Jianfei, Zhigang Mao, Yuliang Tao · 2011
A reconfigurable 64-bit multiply-accumulator(MAC) was presented.Depending on different computation mode,the MAC was capable of performing one 64×64,two 32×32,four 16×16 or eight 8×8 signed/unsigned multiply-accumulate operations.The MAC was vectorized by inserting mode-dependent selectors into partial product(pp) generation and inserting mode-dependent kills in carry chain of the final tree and final adder.In this work,insertion of kills into carry chain of the product reduction tree was avoided by relocating the partial product.Using low-power 4∶2 compressor in partial product tree,both power and area were reduced efficiently.Performances of the MAC,such as speed,power and area,were analyzed.