Design of field programmable gate array based real-time double-precision floating-point matrix multiplier
Yao Chen · Journal of Zhejiang University(Engineering Science) · 2008
A parallel architecture double-precision floating-point matrix multiplier was designed to improve the performance of matrix multiplication.The design was implemented in Xilinx Virtex-4 SX55 field programmable gate array(FPGA).The processing elements in this multiplier were arranged as an array.Up to 25 processing elements can be integrated into a single FPGA device and a peak performance of 3 000 million floating-point operations per second(MFLOPS) can be achieved.For the sparse matrix multiplication often encountered in engineering practices,computation time can be reduced by adding a pre-processing module to avoid the computation of zero element blocks.Experimental results of some dense and sparse matrices with different dimensions showed that this design achieved high computational performance.