A SCHEME OF PARALLEL OR INTERLEAVED MEMORY CONSISTING OF PRIME MODULE MEMORIES
Hu Cui · Chinese Journal of Computers · 1980
In this paper the relationship between memory contention and the number of module in a parallel or interleaved memory generally used in a multiprocessor system is analysed and mathematical models of efficient memory bandwidth for 2n module and prime module are set up respectively. Finally, two hardware schemes of address transformation for the specific prime (2n±1) module are described.