IP Core Design of Single-precision Floating-point to Decimal Conversion
Sun Hong-guo · Journal of Yancheng Institute of Technology · 2011
Using FPGA digital signal processing systems,it always busy with IEEE 754 floating-point to BCD code conversion.Based on the FPGA design,the paper presents a simple shift,addition,subtraction operations as the core of the transformation algorithm,for a state machine strueture with VHDL language,and achieved the use of 732 logic cells and the maximum operating speed of 69.21 MHz in EPEC6Q240C8.