Improved reversible logic synthesis algorithm based on weighted directed graph
Zhijin Guan · Jisuanji gongcheng yu sheji · 2012
To reduce the number of reversible gates used in the reversible logic synthesis,by analyzing the reversible logic synthesis algorithm based on the weighted direction gragh(WDG),the number of transitional gates in the process of function transformation is more and the optimization algorithm is simple,so the concept of efficient complexity-equal primitive output transformation(POT) is proposed,the moving and simplification rules for Toffoli gate sequence are expanded and proven,and the improved synthesis algorithm based on WDG is given.Experimental results show that the improved algorithm can not only reduce the number of reversible gates during circuit generation,but also optimize the generated circuit effectively,the number of gates and control bits is reduced greatly,and the circuit cost is decreased.