A Novel Architecture of FIR Filter Based on FPGA
Jianbiao He, Hongyuan Wang, Guo Yue, Chen Xiao-qian · Microelectronics & Computer · 2008
This paper proposes a novel architecture for implementing various FIR filters expediently in a FPGA chip. And the architecture, which utilizes high-speed pipelined multiple accumulators, can implement different FIR filters with lowest logic resource usage by considering area-speed tradeoffs. Besides, the baseband sharping filter in DVB-C is taken as example to show how to implement FIR filter with this architecture and compare with the traditional implementation architecture for FIR filter, and the result reveals that the restriction of synthesis between the area and speed can be much more efficiently optimized by using the proposed architecture.