Improved Goldschmidt double-precision floating-point divider
Cui Lu-pin · Electronic Design Engineering · 2015
An improved Goldschmidt double-precision floating-point divider is presented to meet the demand of the embedded devices which have a very high requirement for area cost. Two computation stages are employed to carry out this division algorithm. Firstly, a linear-degree minimax polynomial approximation is used to obtain a 15-bit precision estimate of the reciprocal. Then two iterations employing Goldschmidt algorithm specially designed for hardware reuse is performed to gain the final accurate result of division. Finally, the design was implemented by Verilog HDL and prototyped in FPGA. Comparisons with other work show that proposed divider has lower area cost with no performance degradation which meets the requirement of embedded microprocessor.