Design and Implementation of Fractional Delay FIR Filte Based on FPGA
Guanghui Chen, Yicheng Zeng · Microcomputer Information · 2008
Fractional delay filter is able to change its frequency response. But it is sensitive to its coefficients and its coefficients are not symmetric. So much more hardware resources is used to implement the fractional delay FIR filter than the FIR filter. FPGA is rich in logic resource. Therefore it can reach the need of design the fractional delay FIR filter. Based on more excellent arithmetic, the distributed arithmetic and canonic signed digit encoding method are presented to design fractional delay filter. Multiplication operation is transformed to look-up table operation and combining with pipelining technology to reduce hardware resources using and improve processing speed, based on distributed arithmetic. Canonic signed digit encoding makes the zeros of the binary digital which express the coefficients of the filter most. That will reduce scale of hardware greatly and improve operation speed. We can see both of the two methods are viable and high efficiency from the results of simulation.