A Novel Architecture Prototype of Space Solid-State Recorder
Zhensong Wang · Dianzi xuebao · 2008
To meet the future demands of earth observation satellites,this paper presents a novel architecture and describe the implementation of a prototype named Space Solid-State Recorder with several Memory Modules(MMs) connected by high-speed serial links.The MM utilizes an FPGA and DDR SDRAM to boost throughput,and adopts a featured SDDA(Single-Data-bus,Double-Address-bus) storage topology to manage and control these memory chips efficiently.Through high-speed serial transceivers embedded in the FPGA chip,several MMs interconnect with each other to form the Space Solid-State Recorder.To ensure the quality of serial links,a multilayer communication interface protocol stack that consists of a physical layer,link layer and message layer is proposed.As a result,the MM can provide storage capacity of 8GB,and its memory bandwidth approaches 3.2GBps.Furthermore,the physical bandwidth of the communication interface can reach up to 25Gbps.Moreover,the bit error rate(BER) of the interface in Space Solid-State Recorder system is below 10-11.