The Basic Pipeline of CPU Realized by Verilog HDL
Jiangang Wu · Acta Scientiarum Naturalium Universitatis Neimongol · 2004
The basic pipeline of CPU is realized by hardware description language (Verilog HDL).Some data correlation is solved by a directional technique.The control correlation is also considered and settled. The inner structure of CPU pipeline is shown at register level. The dynamic execution of pipeline can be observed by wave drawing, which is generated by the pre-simulator.