Microarchitecture-Level Power Modelling and Analyzing for High-Performance Microprocessors
Yong Wang · Chinese Journal of Computers · 2004
Power dissipation is becoming a serious challenge to microprocessor design, which requires to consider power and performance trade-offs during architecture design phase. Two baseline architecture models with single clock and multi-clock domains respectively are presented based on the Itanium 2 microprocessor architecture. The circuit characteristics are abstracted at microarchitecture level and a microarchitectural peak power estimation model is implemented. An event-scheduling algorithm is presented to support the simulation of the multi-clock-domain systems’. The dynamic power simulation model is implemented based on the IMPACT simulation engine. Compared with similar model Wattch, the peak power estimation accuracy is improved by 3% and the simulation speed is improved by 42%. Experiment is also made to demonstrate the power efficiency of multi-clock-domain system. In one scenario of multi-clock and multi-voltage control, the power and energy are reduced by 21% and 38% respectively with acceptable performance loss. This power model is suitable for architecture-level low power design.