Implementation of 32-bit Single Precision Floating Point Multiplier Based on FPGA
Hua Dang · Modern Electronic Technique · 2005
Using Verilog HDL,a design of 32 b single precision floating point multiplier based on FPGA is presented.By using a structure of Wallace trees and Booth algorithm,the speed of multiplier has been improved.The software of Altera Quartus II 4.1 is used for performing the wave simulation of the multiplier with EPF10K100EQ2401 device.The multiplier is synthesized with 0.5 CMOS technology.