On a Design of High - speed FIr Digital Filter in VLSI
Hua Bing Zhu · Journal of Chongqing Polytechnic College · 2005
In this paper, a VLSI design method for high - speed FIR digital filter is presented. The FIR digital filter adopts a parallel filter architecture based on fast FIR algorithms(FFAs) , improving the filter speed. In addition, the architecture is combined with algorithmic strength reduction to reduce hardware overhead and power consumption. Experiments show that the area and speed restriction of the synthesis can be flexibly optimized by using the improved algorithm of the proposed FIR filter architecture. The method can be used as VLSI realization of digital filter module wit highspeed and hardware - overhead.