A Study on Dynamic Time Warping Algorithm and Its ASIC Implementation
Qian Wang · 2004
By analyzing the Dynamic Time Warping (DTW) algorithm, a systolic array architecture for computations in DTW is described. Results from simulation show that the parallel processor array can finish calculation in M+N-1 clock cycles. The new algorithm requires less operation time than the serial algorithm based on general processors, which need 3pMN/2 clock cycles. The parallel algorithm can be implemented in ASIC.