A High-speed Direct Digital Frequency Synthesizer with Mixed-rotation Structure in 0.35 μm CMOS
Kaihong Zhang · Research & Progress of SSE Solid State Electronics · 2009
This paper presents a novel implementation of a 400 MHz direct digital frequency synthesizer based on mixed-rotation architecture in 0.35 μm CMOS technology.At the algorithmic level,the π/4 rotation operation required is divided into two steps.The first rotation is implemented by CORDIC algorithm and the second rotation is achieved by multiplier.The CORDIC algorithm is realized in pipeline and carry-save arithmetic.At the same time,the pipeline structure is used to achieve an accumulator,so the overall performance is improved.At the transistor level,DPL(double-pass-transistor logic) is employed to implement basic unit and reduce the delay.The measured SFDR is 76.47 dB with an output frequency of 80 MHz at a clock frequency of 400 MHz.The DDFS is fabricated in 0.35 μm N-well 2P3M CMOS process.The area of the chip is 3.4 mm×3.8 mm.