Design of Excellent CMOS Integrated Voltage Comparator
Xinghua Fu · Modern Electronics Technique · 2009
A comparator can compare an analog signal with a referential signal and get a binary system signal.The pre-amplified and locked circuit is used and improved for designing a high precision and high speed comparator.Then,the design of circuit and layout and the validation of layout are completed under Cadence based on CSMC 0.5 μm CMOS process.After simulation,the gain of the design is 85.588 4 dB,the frequency bandwidth is 94.8 MHz,the rise delay time is 5.7237 4 ns,the down delay time is 5.429 17 ns and the offset voltage of import is 640.17 μV.It is fit for high speed system such as A/D.