Techniques of Leakage Current Optimization Based on Don't Care Bits in Test Vectors
Wang Wei · Dianzi xuebao · 2006
It is well-known that leakage power dissipation caused by leakage current in CMOS circuits during test periods has become a significant part of the total power dissipation.It is important to reduce leakage power to improve battery life in portable systems employing periodic self-test,to increase reliability of test and to reduce test-cost.This paper first analyzes leakage current,and introduces the transistor stacking effect relevant to it.Then,we present a method based on don't care bits(X) in test vectors and using the genetic algorithm to optimize leakage current in IC test.Experimental results indicate that this method can effectually optimize leakage current of combinational circuits and sequential circuits during test,and it doesn't lose fault coverage.