The design of an IEEE 802.11b baseband processor with reduced hardware complexity
Hongyi Chen · Journal of Tsinghua University(Science and Technology) · 2005
A low-hardware-complexity baseband processor was designed to reduce the cost of the IEEE 802.11b WLAN system. The baseband processor includes synchronization, acquisition, and complementary code keying (CCK) demodulation. The correlator uses a transposed architecture for signal acquisition and synchronization. The antenna lock technique during acquisition is also described. The CCK demodulator is based on a Fast Walsh Transform (FWT) block, with a novel algorithm used to reduce the hardware complexity. After simulation and verification, the chip was designed using 0.25 μm TSMC digital CMOS technology. The design has about 320 000 gates and a chip area of about 13 mm~2. The simulation results show that the design satisfies all the design requirements.