Design of Three-stage Error Amplifier for LDO
Zonggui Wu · Modern Electronics Technique · 2010
In order to promote LDO in the low power supply voltage environment application,its stability is enhanced,using SMIC 0.35 μm N trap process,a three stage error amplifier with single Miller capacitor frequency compensation,which is suitable for internal error amplifier in LDO is designed and realized.simulation results indicate that this error amplifier can operate under a wide range of power supply(2.5～6.5 V),quiescence current is small,open-loop voltage gain is about 112.16 dB,phase margin is about 89.03°,Gain-Bandwidth Product is about 6.04 MHz,common mode rejection ration is about89.3 dB,power supply rejection ration is about 104.8 dB.