An Efficient FPGA Implementation of AES Algorithm
Jun Wei Yu · Microelectronics & Computer · 2005
On description of the flow of encryption and decryption of AES algorithm (Rijndael), the implementation of S-box is optimized by using composite field arithmetic, the architecture of MixColumns and InvMixColumns is simplified, and the high-speed and efficient implementation with 6 stages of pipeline on FPGA is presented.