A Low Power Design of 2D DCT/IDCT Processor
Bo Shen · Research & Progress of SSE Solid State Electronics · 2007
In this paper a low power 2D DCT/IDCT processor is presented.This processor uses Loeffler's fast algorithm to reduce the power consumption.In addition,zero bypassing,clock gating and truncation are used to reduce the switching activities and the power consumption.Constant coefficient multiplier is a very important part of 2D DCT/IDCT processor.This paper also presents a low power and constant coefficient multiplier with CSD coding and Wallace Tree addition algorithm.The multiplier adopts truncation and variable correction technologies which improve the performance of 2D DCT/IDCT processor significantly.The 2D DCT/IDCT processor is synthesized in SMIC 0.18 μm Technology.The proposed design has a measured power dissipation of 14.971 mW and area of 341 212 μm2 at 100 MHz.It is more power-efficient than other previously reported 2D DCT/IDCT processor designs.