Design and Optimization of a Fast Floating Point Adder
Yuzhuo Fu · Microelectronics & Computer · 2004
In this paper, we present a novel design of IEEE compliant single precision floating point adder. The adder achieved high performance up to 300MHz under 0.18μm technology by using various optimization techniques, such as two data path separation, three pipeline stages, PN encoder, reduced IEEE rounding modes and parallel prefix adder etc.