Successive approximation register ADC for monolithic vacuum sensor
Jiaqi Wang · Dalian Ligong Daxue xuebao · 2009
A 10-bit successive approximation register analog-to-digital converter(ADC)is presented for monolithic vacuum sensor.Rail to rail comparator is achieved by paralleling two complementary comparators.Offset cancellation circuit is included to improve the precision of the ADC.The circuit is fabricated in a 0.5 μm 2P3M standard CMOS process.The system clock frequency is 20 MHz and the input voltage changes from 0 to 3 V.The effective chip area is 2 mm2.The signal to noise and distortion ratio of 56.4 dB and the spurious-free dynamic range of 69.2 dB are achieved with 4.6 kHz sinusoid wave and 1.25 MS/s sample rate.The power dissipation is 3.1 mW at 3 V supply voltage.The proposed ADC meets the requirements of high linearity and low power dissipation.