Low Power and High-Speed Parallel Multiplier Design Using Modified Booth Wallace Tree
Song Lian-guo · Dianzi qijian · 2007
A low power and high-speed 24×24-b signed fixed point multiplier with modified booth encoder and wallace tree for FFT unit in DAB SOC is presented. An 18.81-ns multiplication time is achieved at 50 MHz, by optimizing modified signed extension algorithm, (k:2)compressors, connection algorithm and partition method of final adder. This multiplier has been verified in FPGA and implemented in chartered 0.35 micron CMOS standard cell technology, with its frequency being 50 MHz and its area 14 329.74 gates, power 24.69 mW. This architecture is compared with some other architectures using the same technology, and the result shows that it is effective and efficient.