Reconfigurable Algorithm Design for Low-Power Consumption Design
Huang Qing-hu · Journal of Liuzhou Teachers College · 2014
In order to improve the operational power consumption of logic function chips,this paper designs a logic function reconfigurable algorithm for low-power consumption. First,it splits the traditional logic function design and converts it to low-power consumption reconfigurable design. Then,it elaborates the design methods and principles in detail. From theoretical and experimental perspectives,it analyzes and testes the performance and cost of low-power reconfigurable algorithm,and presents the power saving degree,as well as the cost of logic resources design and operating speed.