Design of Structure Optimization for Flagged Prefix Adder
Jianxiong Zhang · Jisuanji gongcheng · 2010
Flagged prefix adder has fast operation speed,but it has the disadvantage of large area.In order to meet the requirement of floating-point multiply and add cellar area for practical application,this paper gets 51 bit flagged prefix adder based on Kogge-stone tree structure by optimizing its structure.It uses module cascading to reduce the number of operation unit,attains the goal of reducing floating-point multiply,adding cellar area and decreasing power consumption.Under TMSC 0.18 μm technology,area,power and key path delay of this 51 bit adder are decreased respectively by 10%,10.5% and 6.4%.