A low-power ternary D-type flip-flop design based on clock-gating technique
Lunyao Wang · Journal of Circuits and Systems · 2006
Based on ternary D-type flip-flop, a low-power ternary clock-gating D-type flip-flop is proposed. The proposed design reduces power dissipation by restraining the redundant triggered actions of the flip-flop. PSPICE simulation shows that this flip-flop has a correct logic function. Compared with ternary D-type flip-flop, this design reduces power dissipation significantly when input signals have low switching activity. Furthermore, the proposed construction can be extended to the design of multiple valued flip-flops with a higher radix easily.