VLSI implementation of a 32bit embeddedreduced-instruction-set-computer
Hao Min · Semiconductor Technology · 2003
A 32bit embedded RISC microprocessor designed for low-power, low-cost and high-speed is described. The chip implements the ARM V4 instruction set. Based on ARM7TDMIframework, this microprocessor takes the advantage of Harvard architecture and implements a 5-stage pipeline. It also utilizes the improved pipeline hazard control and exception handle circuit forthe fluent flow of pipeline. Compared with commercial ARM7TDMI implemented on 0.35mm CMOSprocess, the chip can achieve the same speed on 0.6mm CMOS process, while the CPI decreases 26%,MIPS increases 36%. The whole design has been tested successfully under Aptix System ExplorerMP3CF hardware verification platform and taped out on CSMC 0.6mm CMOS process.