Design of a 32-bit Divider Based on FPGA
Junhua Wang · Informatization Research · 2010
This paper introduces a method of designing a 32-bit divider based on the programmable logic device FPGA and VHDL language. The divider can operate with sign decimal and unsign decimal. The divider is designed by timing sequence method which saves Les. Shifting,comparing and subtraction are main operations in the design. Because the program is optimized,the language is easy to read and understand. The arithmetic is simple and the division isn't achived by module and hiberarchy. Using QuartusⅡ of Altera,accurate compiling is carried out and waveforms are provided.