Design and Implementation of a Decimation Filter Multiplexing Algorithm Based on IP Core
Fang Cao · Radio Engineering · 2010
A multiplexing decimation filter based on FIR IP core is designed and implemented.The parameters of FIR IP core can be changed easily for different kinds of filter design,so the FIR filter design is achieved by changing the parameters of the FIR IP core.An example of multiplexing decimation filter with 128 channels of signal is given.With factors such as filter characteristics and resource allocation of FPGA taken into consideration,an optimum decimation filtering and multiplexing module based on FIR IP core is built to achieve the design and implementation of the multiplexing decimation filter with 128 channels of signal.