Design of CPU with Cache and Precise Interruption Response
Liu Qiu-ju · Research and Exploration in Laboratory · 2012
In this paper the design of CPU with Cache and precise interruption response was proposed.15 of the MIPS instruction set were selected as the basic instruction for the CPU.By using 5 stage pipeline,the instruction Cache,data Cache and precise interruption response were realized.The test results show that the scheme meets the design requirements.