Study of Floating-point Multiply-Add Unit Latency Effect on Floating-point Performance
He Ju · Jisuanji gongcheng · 2013
Considering the shortcoming that the Fused Multiply-Add(FMA) unit increases the latency of separate floating-point add/subs tract and multiply operations,the effect of FMA unit latency optimization,reducing the latency of separated floating-point add/subtract and multiply operations from 6 cycles to 4 cycles,on floating-point performance is studied.Based on a homemade processor with FMA unit,the RTL design is modified.The effect of the optimization on floating-point performance is estimated after running SPEC CPU2000 floating-point benchmarks on the hardware emulation acceleration platform.As the results turned out that the floating-point performance of the benchmarks is all improved 5.25% at most and 1.61% on average,proving that such optimization in favor of floating-point performance promotion.