Serial Circuit Architecture for Power-Sum in GF(2~m)
Xintian Li · 2006
An iterative algorithm for computing power-sum in GF(2~m) is proposed using polynomial basis.During each iteration step,one bit-vector polynomial multiplication and reduction modulo of irreducible polynomial are computed.Based on this algorithm,a new serial power-sum circuit architecture is designed,with area complexity of O(m),and throughput of one result per m clock cycle. Compared with existing power-sum architectures,the proposed method has small area complexity,thus well is suited to VLSI design of applications with small chip area requirements.The power-sum architecture can be used to compute exponentiations and squares.