Design of a Combined Serial/Parallel FIR Digital Filter Based on Distributed Arithmetic
Yali Qin · Research and Exploration in Laboratory · 2012
This paper focuses on the design of the combined serial/parallel distributed arithmetic-based FIR digital filter with parallelism N=2,for which a novel architecture of FPGA implementation is proposed.A new module of shift-accumulate is designed to accumulate the outputs of two look-up tables,and the corresponding control circuit is configured by shift-register.A series of FIR filters with an input precision of eight is designed.These proposed filters have been simulated and synthesized with Quartus II 7.1 and implemented with an EPF10K70RC240-4 FPGA device.The result shows that the structure can efficiently reduce the process of critical path and modular design,and the performance can be improved.