A Design of Digital Delay Line Based on FPGA
Ke Xu · Microcomputer Information · 2010
The design of a new digital delay line(DDL) is introduced in this paper.This DDL can achieve the time delay by the step of 0.1ns, and the delay duration can be easily expanded to more than 10ms in this scheme.The delay circuit was constituted by a wide delay unit and a narrow delay unit.The wide delay unit was build up by user-defined counters, while the narrow delay unit make up of an IODELAY unit.Its designed code has been compiled and simulated on FPGAdv software.It had been applied to control the delay of the radar signal envelop in radar altimeter simulator successfully.