THE HARDWARE REALIZATION OF FLOATING-POINT MULTIPLIER WITH VHDL
Guofeng Li · Journal of Nankai University · 2002
In this paper, we address a method of the hardware realization for floating point multiplier with VHDL. That is, the multiplier is described with VHDL, realized on FPGA. We have done the simulation in MAX+plus2 and got very good results. We can do multiplication of arbitrary bits with it.