18×18-bit radix-4 multiplier embedded in FPGA and based on modified Booth algorithm
Lei Guo · Modern Electronics Technique · 2012
A multiplier embedded in FPGA was designed.It can perform 18×18-bit signed number or 17×17-bit unsigned number multiplying operation,and is based on modified Booth algorithm.In order to improve the speed of the multiplier,a new structure of Booth encoder and partial product was proposed,and 9-2 compressed tree and carry lookahead adder(CLA) were optimized.TSMC 0.18 μm CMOS technique is adopted in this multiplier.Its critical path delay is 3.46 ns.