The Summary of RTL to GDSII Design Flow
Yanjun Zhang · Microprocessors · 2009
RTL to GDSII design flow is briefly described from environment setting,constraint checking,clock plan,synthesis,floorplan and power plan,placement and optimization with DFT,clock tree synthesis,post-CTS optimization,routing and optimization,physical verification,RC extraction,static timing analysis,functional verification,formal check,automatic test pattern generation,etc.