Survey on Interconnects of Networks-on-Chip and its solutions
Jianhao Hu · China Integrated Circuit · 2009
Interconnect buses in deep-submicron network-on-chip (NoC)designs suffer from three major problems: power dissipation,propagation delay,reliability,and all of the three problems have become bottlenecks of NoC performance improvement. Taking into account flexibility and comprehensive ability of bus coding,this paper firstly discusses bus coding for power,delay,and reliability respectively. And finally introduces a unified bus coding framework to answer these challenges as a whole.