Research and Implementation of FPGA-Based High-Speed 2D-DCT
Yu PeiLing · Computer Engineering and Science · 2012
This paper presents a high-performance 2D discrete cosine transform (DCT) processor based on distributed algorithms(DA),which uses the field programmable gate array (FPGA) to implement the JPEG encoder. This processor has none multiplier. An improved DA structure is designed and the pipelining style is applied to the data flow. The FPGA implementation and simulation results show that this design can achieve a higher operation speed than the traditional fast DCT algorithm.