Header error control functional blocks for design reuse
Hongyi Chen · Journal of Tsinghua University(Science and Technology) · 1999
Design reuse is very improtant in improving design efficiency while IC complexity increases. Functional block is one useful way for design reuse. This article describes reuse based functional block design flow through developing the header error control (HEC) processing block set. A design flow with block modeling, algorithm analysis, structure planning, behavioral description, verification, synthesis and documentation is used to design the HEC block set. Compared with traditional design flow, this flow emphasizes model integrality, importance of different algorithm analysis for hardware implementation, generality and readability for description, and integrality of documentation. This flow fits for design reuse oriented block development, and the HEC block set can be easily reused in the asynchronous transfer mode (ATM) chip design.