The Research of Viterbi Decoder with FPGA in W-CDMA System
Lin Jian-hui · Journal of Ningbo University · 2004
In broadband CDMA system, convolution data with K=9 constrain length should be decoded in real time. A new topic is presented on how to realize short delay, simple structure and low memories of Viterbi decoder. Some new technologies are proposed, such as splitting memories of path metric,short tracing back under best suitable state, storing paths message circularly, which leads to the advantage with low delay and memories. The performance of Viterbi decoder implemented with FPGA is also tested.